1. Field of the Invention
The present invention relates to a method for supporting the design of a semiconductor integrated circuit and a system using the same method and, more particularly, to a method for supporting the design of the semiconductor integrated circuit for the prediction of the performance of a large-scale integrated circuit (LSI) and a system using the same method.
2. Description of the Prior Art
With the increase in the size of semiconductor integrated circuits (LSIs), time required for design has become so long that it is necessary to predict LSI performance at the earliest possible stage. Despite such requirements, as a result of higher transistor element performance due to a request for using it under the condition of higher frequency, however, the performance of the LSI largely depends on wiring delay, which means that LSI performance cannot be calculated until the very late stage of laying out the wiring.
A method proposed for calculating LSI performance, is the (Stanford University System Performance Simulator) (SUSPENS) model (H. B. Bakogulu et Al. ISSCC'87, pp. 308-309, 439-440, 1987). With this model, LSI performance as a whole is estimated with one estimate from technology parameter and circuit parameters.
Furthermore, this technology is disclosed in Japanese Patent Laid-Open No. 7-7142, Japanese Patent Laid-Open No. 8-77243, Japanese Patent Laid-Open No. 8-77227, Japanese Patent Laid-Open No. 7-262264, Japanese Patent Laid-Open No. 7-263560, and Japanese Patent Laid-Open No. 6-37184.
In the technology disclosed in Japanese Patent Laid-Open No. 7-7142, delay time is calculated from a logical description, the most appropriate value of the physical wiring configuration of a transistor is calculated by using the delay time, and then wiring is laid out on the layout of the cell base from this calculation result.
The technology disclosed in Japanese Patent Laid-Open No. 8-77243 is such that an effective wiring length is determined from a delay value for capacity load and a delay value for sufficiently long wiring. The precision of calculating the load capacity that is connected to the logic gate is improved by using this efficient wiring length, and the precision of the calculation of the delay value is improved.
In the technology disclosed in Japanese Patent Laid-Open No. 8-77227, processing for reducing clock skew is easily automated by differentiating the length of clock signal wiring for a cell that requires the clock signal, and registering, beforehand, a plurality of cells having different times for delaying the clock signal.
In the technology disclosed in Japanese Patent Laid-Open No. 7-262264, a comprehensive appropriation is attempted by simultaneously dividing logic cells that conflict while holding divided information.
In the technology disclosed in Japanese Patent Laid-Open No. 7-263560, an appropriate input/output buffer is selected based on semiconductor integrated circuit specifications, and the power consumed by the semiconductor integrated circuit is reduced and the chip area is decreased so that a semiconductor integrated circuit having high area efficiency can be designed.
In the technology disclosed in Japanese Patent Laid-Open No. 6-37184, specification data is input; a design is laid out based on data; channel usage efficiency, chip size, signal delay value, and capacity are calculated based on the layout design; and it is judged whether or not the calculation result satisfies the required specification so that evaluation precision at the initial stage of semiconductor integrated circuit design is improved.
In the SUSPENS model, however, since R.sub.int.times.C.sub.int.times.D.sub.c.sup.2 /2 is assumed as the clock skew value (refer to the document on the SUSPENS model, p440, Table 2, Step 8), calculation is not satisfied for a detailed LSI following the 0.35 .mu.m rule, in which the ratio of wiring delay is increased. When, for example, the 0.35 .mu.m rule is applied, a 15 mm angle chip, a wiring resistance of 0.125 .OMEGA./.mu.m, a wiring capacity of 0.17 fF/.mu.m (wiring width of 0.4 .mu.m, wiring pitch of 1 .mu.m, wiring film thickness of 0.6 .mu.m, and interlayer film thickness of 1 .mu.m) are assumed, and 0.125.times.0.17.times.10.sup.-15.sub.x (15.times.10.sup.3).sup.2 /2=2.4 nsec. is calculated, but in actuality, the value is about 200 psec. so the calculation differs by one digit. In other words, the calculation value is about 10 times the actual value.
Furthermore, in the SUSPENS model, Lenz's index p is used, which is said to depend on the circuit architecture. With an increase in the scale of the LSI, however, for example, a different architecture circuit block, a CPU core, a first cache memory, and a second cache memory are provided on one chip so that the conventional Lenz's index cannot be used for the change in such architecture.
This is because, in the end, the SUSPENS model evaluates the circuit performance as a whole, in principle, so that the performance thereof cannot be evaluated in a case in which the circuit structure is changed.
Even when Lenz's index is defined for a new architecture, if the integration of the LSI is advanced, and then a different circuit block is mounted on the same chip, a new Lenz's index must be determined again. In other words, as long as the SUSPENS model is used, it is very difficult to predict the performance of the LSI in the new architecture.
In other words, even when the SUSPENS model is used for design, the operating frequency, chip area, and consumed power of the whole LSI to be designed are calculated, and it is judged whether or not the design satisfies the specification, and no effective information is provided on what aspects should be changed with respect to the change of the design.
Furthermore, the technology disclosed in each of the aforementioned publications is associated with the technology for the performance calculation of the circuit block. No technology is provided for predicting the overall calculation of the semiconductor integrated circuit comprising a combination of a plurality of circuit block at an initial stage of the design.